On Monday Applied Materials said it would more than double its holding in BE Semiconductor Industries (Euronext Amsterdam: BESI), taking it to about 20% of the Dutch bonder maker’s shares. Four days earlier Besi had reported third-quarter orders of €342.6 million, up 96% on a year ago and well above the roughly €298 million analysts expected. And yet by early October the stock had fallen about 40% from its June peak, and Bank of America cut it to neutral. Those three facts don’t fit together unless you separate two questions the market keeps mixing up: whether hybrid bonding becomes the way HBM gets stacked, and when.
The first question is close to settled. The second is where the money is made and lost.
What actually gates a 16-high stack
High-bandwidth memory is a stack of thin DRAM dies sitting on a logic base die, wired together through silicon vias. Today every major supplier joins those dies with thermocompression bonding: tiny solder microbumps between each layer, plus a filler. SK hynix uses mass-reflow molded underfill (MR-MUF), Samsung and Micron have used non-conductive film (TC-NCF). Each bump and each film layer adds height. Stack eight dies and nobody cares. Stack sixteen and the height budget starts to bite, along with heat, because the filler between dies is a poor conductor.
Hybrid bonding removes the bumps and the filler. Copper pads on one die bond directly to copper pads on the next, and the oxide around them bonds too. The stack gets thinner, heat moves more easily between layers (Samsung claimed at Nvidia’s GTC in March that thermal resistance drops by more than 20% against thermocompression), and the pad pitch can shrink far below what microbumps allow. That last point is the one that eventually forces the switch. I/O counts per stack keep rising, and bumps can’t keep up.
The constraint that decides timing is a number set by JEDEC: the maximum package height. It was 720 microns through HBM3E. For HBM4 it went to 775 microns, which was enough for SK hynix to show a 16-high HBM4 sample at CES in January and keep its MR-MUF process for it, with hybrid bonding as the backup. Reports from April and July say the standards body is discussing roughly 900 microns for the next step, with talk of up to 1,000 microns for 20-high HBM5. Every time JEDEC adds height, it buys the incumbent process another generation.
So the bottleneck is real, and it moves. That’s the part the market has trouble pricing.
The memory makers keep pushing the date out
Two years ago the consensus had hybrid bonding arriving with HBM4. It didn’t. All three suppliers passed Nvidia’s HBM4 qualification on thermocompression, and Jensen Huang said in June that all three were moving into mass production. SK hynix placed a 44.2 billion won order for about 15 Hanmi Semiconductor TC bonders in June, and Korean press reports rising demand for Hanmi’s wide TC bonder, built for bigger dies. Bigger dies add capacity without stacking higher.
The July reporting from ZDNet Korea and TrendForce put the earliest likely hybrid bonding insertion at 16-high HBM4E, and even that came with a caveat: a memory executive said 16-high discussions with customers remain limited and 12-high HBM4E should stay mainstream. Nvidia’s own roadmap has been softening on stack height. TrendForce reports it is weighing 8-high and 12-high configurations because 12-high HBM4E supply is tight in a DRAM shortage (a theme we covered in why memory prices won’t come down).
SK hynix was blunt about its own threshold. A senior director at its US arm told a SEMI conference in San Jose on September 9 that the company won’t introduce hybrid bonding in volume until yields reach 90% to 98% and the parts show a three-to-five-year lifespan. At Hot Chips in August the company framed hybrid bonding around stacks of 20 layers or more. That points to HBM5.
None of this means the memory makers have walked away. SK hynix completed validation of a 12-high hybrid bonded stack in April. In March it bought a joint Applied Materials and Besi inline system, about 20 billion won, its first hybrid bonding purchase aimed at mass production, and it is also testing Hanwha Semitech tools. Samsung has Besi machines in development and is testing hybrid bonders from its own affiliate SEMES. Micron hasn’t said publicly which bonding method it will take into HBM4E. The pattern is the same everywhere: buy tools, run them, keep the old process in production until the new one clears the yield bar.
Why the market may misprice the timing
There are two ways to get this wrong, and the share price has done both inside a year.
The first is to treat hybrid bonding as an HBM4 story. That trade put a memory ramp into Besi’s multiple that the memory makers never delivered on schedule.
The second mistake is the one the market may be making now: reading every JEDEC relaxation and every Hanmi order as proof that hybrid bonding in memory is years away and Besi’s growth depends on it. Look at what the company actually reported. Hybrid bonding orders in the first nine months of 2026 were more than double the whole of 2025. It now counts 23 hybrid bonding customers and cumulative demand above 215 systems, against more than 150 at the end of last year. Memory isn’t the only buyer. Logic stacking uses the tools in production today: TSMC’s SoIC, which has taken bond pitch from 9 microns to 6 and targets 4.5 by 2029, AMD’s stacked cache, and chiplet designs that put logic on logic. Revenue was €283.4 million in the quarter, up 114%, with a 65.2% gross margin and €246.6 million of net cash.
The weak spot was guidance. Besi expects fourth-quarter revenue flat with the third, within 5% either way, below the roughly €291 million to €298 million consensus range, and blamed customers’ line readiness rather than cancellations. That is exactly the timing risk in miniature: orders arrive, shipments wait for a fab to be ready.
Then there’s competition. ASML has said it’s studying hybrid bonding, and Bank of America argues that risk isn’t in the price; Besi’s CEO says the two are working together on placement accuracy. Applied has its own Kinex system, ASMPT works with EV Group, and Hanwha and SEMES are building tools for the Korean memory makers. Bernstein still expects Besi to supply three of every four hybrid bonders shipped in 2028. A crowded field in 2030 doesn’t change who has the installed base when HBM finally switches.
Applied’s move on Monday is the clearest outside read on that. It already owned about 9% from April 2025. It has now signed an accelerated share purchase to reach about 20%, subject to US antitrust clearance, says it has no plan to go higher and won’t seek a board seat. The release names hybrid bonding, thermocompression bonding and die-on-wafer, die-on-die and die-on-panel integration as the scope. Lam Research and Applied were both reported in March to have shown takeover interest, and any bid would face a Dutch security review. A 20% holder that turns down a board seat is making a long-dated bet on the technology; a bidder would want the seat.
Where the risk sits
For memory makers the risk is a late, rushed switch. If I/O counts or thermal limits force hybrid bonding into a generation before yields are ready, the supplier that validated earliest wins share and the rest eat yield losses at the worst point in a tight market. SK hynix’s 90% yield rule is a hedge against that.
For equipment makers the risk is the gap. A tool vendor priced for an HBM ramp in 2027 gets a JEDEC height bump and a 12-high mainstream instead, and the revenue line goes flat for a few quarters while the orders sit. TC bonder makers like Hanmi carry the mirror risk: every quarter of delay is good for them, until it isn’t.
For the AI accelerator buyers the risk is quieter. Stack height is a capacity lever. If 16-high and 20-high stacks slip, more capacity has to come from more stacks per package or bigger dies, which puts the pressure on interposers, substrates and wafer starts instead. The broader equipment picture is in our semiconductor equipment outlook, and the technology side is tracked at technologies.org and analysis.org.
The market has priced hybrid bonding as either imminent or distant for memory. The evidence says it’s a staged switch that JEDEC can delay and only yield can finish. Logic is buying the tools now. Memory is buying them to learn.
The date that matters is the first 16-high or 20-high stack a memory maker ships on hybrid bonding in volume, and nobody has named it yet.
This article is analysis, not investment advice.
